[all-commits] [llvm/llvm-project] 3304d5: [RISCV] Add performMULcombine to perform strength-...
Philipp Tomsich via All-commits
all-commits at lists.llvm.org
Tue Feb 7 22:57:46 PST 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 3304d51b676ea511feca28089cb60eba3873132e
https://github.com/llvm/llvm-project/commit/3304d51b676ea511feca28089cb60eba3873132e
Author: Philipp Tomsich <philipp.tomsich at vrull.eu>
Date: 2023-02-08 (Wed, 08 Feb 2023)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
Log Message:
-----------
[RISCV] Add performMULcombine to perform strength-reduction
The RISC-V backend thus far does not provide strength-reduction, which
causes a long (but not complete) list of 3-instruction patterns listed
to utilize the shift-and-add instruction from Zba and XTHeadBa in
strength-reduction.
This adds the logic to perform strength-reduction through the DAG
combine for ISD::MUL. Initially, we wire this up for XTheadBa only,
until this has had some time to settle and get real-world test
exposure.
The following strength-reductions strategies are currently supported:
- XTheadBa
- C = (n + 1) // th.addsl
- C = (n + 1)k // th.addsl, slli
- C = (n + 1)(m + 1) // th.addsl, th.addsl
- C = (n + 1)(m + 1)k // th.addsl, th.addsl, slli
- C = ((n + 1)m + 1) // th.addsl, th.addsl
- C = ((n + 1)m + 1)k // th.addslm th.addsl, slli
- base ISA
- C being 2 set-bits // slli, slli, add
(possibly slli, th.addsl)
Even though the slli+slli+add sequence would we supported without
XTheadBa, this currently is gated to avoid having to update a large
number of test cases (i.e., anything that has a multiplication with a
constant where only 2 bits are set) in this commit.
With the strength reduction now being performed in performMUL combine,
we drop the (now redundant) patterns from RISCVInstrInfoXTHead.td.
Depends on D143029
Differential Revision: https://reviews.llvm.org/D143394
Commit: 656188ddc4075eb50260607b3497589873f373d2
https://github.com/llvm/llvm-project/commit/656188ddc4075eb50260607b3497589873f373d2
Author: Philipp Tomsich <philipp.tomsich at vrull.eu>
Date: 2023-02-08 (Wed, 08 Feb 2023)
Changed paths:
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.rst
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/bittest.ll
A llvm/test/CodeGen/RISCV/rv32xtheadbs.ll
A llvm/test/CodeGen/RISCV/rv64xtheadbs.ll
A llvm/test/MC/RISCV/rv32xtheadbs-invalid.s
A llvm/test/MC/RISCV/rv32xtheadbs-valid.s
A llvm/test/MC/RISCV/rv64xtheadbs-invalid.s
Log Message:
-----------
[RISCV] Add vendor-defined XTHeadBs (single-bit) extension
The vendor-defined XTHeadBs (predating the standard Zbs extension)
extension adds a bit-test instruction (th.tst) with similar semantics
as bexti from Zbs. It is supported by the C9xx cores (e.g., found in
the wild in the Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for XTHeadBs is
available from:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da
Depends on D143394
Differential Revision: https://reviews.llvm.org/D143036
Commit: 19a59099095b3cbc9846e5330de26fca0a44ccbe
https://github.com/llvm/llvm-project/commit/19a59099095b3cbc9846e5330de26fca0a44ccbe
Author: Philipp Tomsich <philipp.tomsich at vrull.eu>
Date: 2023-02-08 (Wed, 08 Feb 2023)
Changed paths:
M clang/include/clang/Basic/BuiltinsRISCV.def
A clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c
A clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
M llvm/docs/RISCVUsage.rst
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/imm.ll
M llvm/test/CodeGen/RISCV/rotl-rotr.ll
A llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
A llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
Log Message:
-----------
[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension
The vendor-defined XTHeadBb (predating the standard Zbb extension)
extension adds some bit-manipulation extensions with somewhat similar
semantics as some of the Zbb instructions.
It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for XTHeadBb is
available from:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da
Depends on D143036
Differential Revision: https://reviews.llvm.org/D143439
Commit: 94888161c7d9133bf6f32ae0d47a4fb0f41985f2
https://github.com/llvm/llvm-project/commit/94888161c7d9133bf6f32ae0d47a4fb0f41985f2
Author: Philipp Tomsich <philipp.tomsich at vrull.eu>
Date: 2023-02-08 (Wed, 08 Feb 2023)
Changed paths:
M llvm/test/MC/RISCV/rv32zba-valid.s
M llvm/test/MC/RISCV/rv64zba-valid.s
Log Message:
-----------
[RISCV] Fix comment for Zba tests. NFC.
The comments in the Zba tests were referring to the "bitmanip base"
extension (i.e., the Zbb). Fix it.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D143534
Compare: https://github.com/llvm/llvm-project/compare/e25b30d90a69...94888161c7d9
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