[all-commits] [llvm/llvm-project] e25b30: [RISCV] Add vendor-defined XTHeadBa (address-gener...

[Philipp Tomsich via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e25b30d90a69846650fa15a3e41a013ea20193ff
      https://github.com/llvm/llvm-project/commit/e25b30d90a69846650fa15a3e41a013ea20193ff
  Author: Philipp Tomsich <philipp.tomsich at vrull.eu>
  Date:   2023-02-08 (Wed, 08 Feb 2023)

  Changed paths:
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    A llvm/test/CodeGen/RISCV/rv32xtheadba.ll
    A llvm/test/CodeGen/RISCV/rv64xtheadba.ll
    A llvm/test/MC/RISCV/XTHeadBa-invalid.s
    A llvm/test/MC/RISCV/XTHeadBa-valid.s

  Log Message:
  -----------
  [RISCV] Add vendor-defined XTHeadBa (address-generation) extension

The vendor-defined XTHeadBa (predating the standard Zba extension)
extension adds an address-generation instruction (th.addsl) with
similar semantics as sh[123]add from Zba.  It is supported by the C9xx
cores (e.g., found in the wild in the Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBa is
available from:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143029