[all-commits] [llvm/llvm-project] b0c313: Revert "[RISCV] Add vendor-defined XTheadBb (basic...

[Philipp Tomsich via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b0c3132226d521d6693608ee76fb3c0dc260ce89
      https://github.com/llvm/llvm-project/commit/b0c3132226d521d6693608ee76fb3c0dc260ce89
  Author: Philipp Tomsich <philipp.tomsich at vrull.eu>
  Date:   2023-02-08 (Wed, 08 Feb 2023)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsRISCV.def
    R clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c
    R clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
    M llvm/docs/RISCVUsage.rst
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
    M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
    M llvm/test/CodeGen/RISCV/imm.ll
    M llvm/test/CodeGen/RISCV/rotl-rotr.ll
    R llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
    R llvm/test/CodeGen/RISCV/rv64xtheadbb.ll

  Log Message:
  -----------
  Revert "[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension"

This reverts commit 19a59099095b3cbc9846e5330de26fca0a44ccbe.


  Commit: 0bda199285954dea3b36539a17ea4a0a5bfa6cb1
      https://github.com/llvm/llvm-project/commit/0bda199285954dea3b36539a17ea4a0a5bfa6cb1
  Author: Philipp Tomsich <philipp.tomsich at vrull.eu>
  Date:   2023-02-08 (Wed, 08 Feb 2023)

  Changed paths:
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/CodeGen/RISCV/bittest.ll
    R llvm/test/CodeGen/RISCV/rv32xtheadbs.ll
    R llvm/test/CodeGen/RISCV/rv64xtheadbs.ll
    R llvm/test/MC/RISCV/rv32xtheadbs-invalid.s
    R llvm/test/MC/RISCV/rv32xtheadbs-valid.s
    R llvm/test/MC/RISCV/rv64xtheadbs-invalid.s

  Log Message:
  -----------
  Revert "[RISCV] Add vendor-defined XTHeadBs (single-bit) extension"

This reverts commit 656188ddc4075eb50260607b3497589873f373d2.


  Commit: b4431b2d945b6fc19b1a55ac6ce969a8e06e1e93
      https://github.com/llvm/llvm-project/commit/b4431b2d945b6fc19b1a55ac6ce969a8e06e1e93
  Author: Philipp Tomsich <philipp.tomsich at vrull.eu>
  Date:   2023-02-08 (Wed, 08 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

  Log Message:
  -----------
  Revert "[RISCV] Add performMULcombine to perform strength-reduction"

This reverts commit 3304d51b676ea511feca28089cb60eba3873132e.


Compare: https://github.com/llvm/llvm-project/compare/94888161c7d9...b4431b2d945b