[all-commits] [llvm/llvm-project] 36cfe2: AMDGPU: Try to unfold fneg source when matching le...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 36cfe26a5288d99e66c75d82989d154874999b98
      https://github.com/llvm/llvm-project/commit/36cfe26a5288d99e66c75d82989d154874999b98
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2023-02-02 (Thu, 02 Feb 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
    M llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
    M llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
    M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll

  Log Message:
  -----------
  AMDGPU: Try to unfold fneg source when matching legacy fmin/fmax

This is NFC as it stands, since other combines will effectively
prevent this from being reachable. This will avoid regressions in a
future change which tries to make better use of select source
modifiers.

Didn't bother with the GlobalISel part for now, since the baseline
combine doesn't seem to work on the existing test.


  Commit: 149e8abbd9d86ff67ef0daf8b70fccaab056cae9
      https://github.com/llvm/llvm-project/commit/149e8abbd9d86ff67ef0daf8b70fccaab056cae9
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2023-02-02 (Thu, 02 Feb 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h

  Log Message:
  -----------
  AMDGPU: Factor out fneg fold predicate function


  Commit: 3a01b4a93df22bf4e0c5e49b756f92f96df3874c
      https://github.com/llvm/llvm-project/commit/3a01b4a93df22bf4e0c5e49b756f92f96df3874c
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2023-02-02 (Thu, 02 Feb 2023)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll

  Log Message:
  -----------
  AMDGPU: Regenerate test checks

Use right prefix order to get merging.

Also drop -verify-machineinstrs and add -amdgpu-enable-delay-alu=0


  Commit: 0f8b3b97fd38041aa3f18966edd95e6cc00f1a54
      https://github.com/llvm/llvm-project/commit/0f8b3b97fd38041aa3f18966edd95e6cc00f1a54
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2023-02-02 (Thu, 02 Feb 2023)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll

  Log Message:
  -----------
  AMDGPU: Add additional tests for is.fpclass legalization


  Commit: b3813a882ccce00f4af0c3fa40827e6bdf07fd14
      https://github.com/llvm/llvm-project/commit/b3813a882ccce00f4af0c3fa40827e6bdf07fd14
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2023-02-02 (Thu, 02 Feb 2023)

  Changed paths:
    M llvm/test/CodeGen/X86/is_fpclass.ll

  Log Message:
  -----------
  X86: Add some baseline tests for broken is.fpclass handling with DAZ

If DAZ is enabled, a test against fcZero is not equivalent to a compare
with 0.


Compare: https://github.com/llvm/llvm-project/compare/10d85dc75468...b3813a882ccc