[all-commits] [llvm/llvm-project] 089bfe: [RISCV][Driver] Add -mrvv-vector-bits= option simi...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 089bfedfb828c2675f3cc57d6ecac1a87ca243a1
      https://github.com/llvm/llvm-project/commit/089bfedfb828c2675f3cc57d6ecac1a87ca243a1
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-02-02 (Thu, 02 Feb 2023)

  Changed paths:
    M clang/docs/ReleaseNotes.rst
    M clang/include/clang/Driver/Options.td
    M clang/lib/Driver/ToolChains/Clang.cpp
    A clang/test/Driver/riscv-rvv-vector-bits.c

  Log Message:
  -----------
  [RISCV][Driver] Add -mrvv-vector-bits= option similar to -msve-vector-bits=

This option will control the vscale min/max.

I have left out the '+' support that SVE supports for now. We already
have minimum controlled by the Zvl*b extension so this didn't seem that
useful.

I've added "scalable" from SVE to allow the option to be cancelled later on
command line. Though this name might make less sense for RISC-V since
the word "scalable" does not appear in the V spec. Maybe something like
"unknown" or "runtime" or "variable" would be better?

In addition to "scalable", 64, 128, 256, 512, ..., 65536, I have added an extra
value "zvl" that will use the value from Zvl*b as the min and max.
This avoids repeating the numeric value in two places or to get
min/max from -mcpu.

The primary effect of this option today is simplification of stack
address calculations for RVV vectors and avoiding the use of
vrgatherei16 in some cases if we know there are less than 256 elements.

Future patches may add something similar to the arm_sve_vector_bits
attribute to allow RVV vectors to be used in structs and global
variables.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D142144