[all-commits] [llvm/llvm-project] 7cd725: [RISCV] RISCVDAGToDAGISel::selectShiftMask to shif...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7cd725858b4b67ca44a8d34483c28b5e12a4c733
      https://github.com/llvm/llvm-project/commit/7cd725858b4b67ca44a8d34483c28b5e12a4c733
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-12-29 (Thu, 29 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    A llvm/test/CodeGen/RISCV/shift-amount-mod.ll

  Log Message:
  -----------
  [RISCV] RISCVDAGToDAGISel::selectShiftMask to shift by (sub size-1, X).

If the shift amount is (sub C, X) where C is -1 modulo the size of
the shift, we can replace the sub with a NOT.

We could also use XORI X, size-1, but NOT would work better with
c.not from the future Zce extension.