[all-commits] [llvm/llvm-project] a63b72: [RISCV] Use SUB instead of XOR in lowerShiftLeftPa...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a63b7247299ce6edfbbf47c4a2773e5ca7eb7f11
      https://github.com/llvm/llvm-project/commit/a63b7247299ce6edfbbf47c4a2773e5ca7eb7f11
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-12-29 (Thu, 29 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/alu64.ll
    M llvm/test/CodeGen/RISCV/rotl-rotr.ll
    M llvm/test/CodeGen/RISCV/rv32zbs.ll
    M llvm/test/CodeGen/RISCV/shift-amount-mod.ll
    M llvm/test/CodeGen/RISCV/shift-masked-shamt.ll
    M llvm/test/CodeGen/RISCV/shifts.ll
    M llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
    M llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll

  Log Message:
  -----------
  [RISCV] Use SUB instead of XOR in lowerShiftLeftParts/lowerShiftRightParts./

isel is now capable of turning the SUB into XOR for shift amounts.
Though it uses NOT instead of XOR with ShiftSize-1.

By using SUB during lowering we enable more DAG combines with
other arithmetic on the shift amount.