[all-commits] [llvm/llvm-project] 1578c6: [NFC][SROA] Variably-indexed load: add test variat...

[Roman Lebedev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1578c670ff3c0058ac6043e55e40d37d260937bd
      https://github.com/llvm/llvm-project/commit/1578c670ff3c0058ac6043e55e40d37d260937bd
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2022-12-23 (Fri, 23 Dec 2022)

  Changed paths:
    A llvm/test/Transforms/SROA/widen-load-of-small-alloca-special-cases.ll
    A llvm/test/Transforms/SROA/widen-load-of-small-alloca-with-zero-upper-half.ll
    M llvm/test/Transforms/SROA/widen-load-of-small-alloca.ll

  Log Message:
  -----------
  [NFC][SROA] Variably-indexed load: add test variation w/ upper half of alloca being zeros

This is the actual pattern i'm looking at.


  Commit: aad725928d767243dff1fc66f26b7afb17e29865
      https://github.com/llvm/llvm-project/commit/aad725928d767243dff1fc66f26b7afb17e29865
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2022-12-23 (Fri, 23 Dec 2022)

  Changed paths:
    A llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll

  Log Message:
  -----------
  [NFC][Codegen][X86] Add codegen test coverage for the variably-indexed load of alloca w/zero upper half


Compare: https://github.com/llvm/llvm-project/compare/f952bc05fda6...aad725928d76