[all-commits] [llvm/llvm-project] 9b227c: [RISCV] Check the sign bits of the input of RISCVI...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9b227cb1f536829ce109f7334beceb71f804d58b
      https://github.com/llvm/llvm-project/commit/9b227cb1f536829ce109f7334beceb71f804d58b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-12-21 (Wed, 21 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  [RISCV] Check the sign bits of the input of RISCVISD::ABSW in computeNumSignBitsForTargetNode.

We created a SIGN_EXTEND_INREG when we created the ABSW so the
input should have 33 sign bits, but check it to be safe.