[all-commits] [llvm/llvm-project] 9fdf21: [RISCV] Add test cases for i8/i16 abs followed by ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9fdf21f3d07d5efafec4334b1b4d200bc7811c05
      https://github.com/llvm/llvm-project/commit/9fdf21f3d07d5efafec4334b1b4d200bc7811c05
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-12-21 (Wed, 21 Dec 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/iabs.ll

  Log Message:
  -----------
  [RISCV] Add test cases for i8/i16 abs followed by zext.

The andi, zext.h and slli+srli shift pairs at the end of the generated
output are unnecessary if the input is sign extended.