[all-commits] [llvm/llvm-project] 564d47: [AMDGPU][GFX8][DOC][NFC] Update assembler syntax d...

[dpreobra via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 564d47db9eb031ae1269f66311f6cb0c47153d1d
      https://github.com/llvm/llvm-project/commit/564d47db9eb031ae1269f66311f6cb0c47153d1d
  Author: Dmitry Preobrazhensky <dmitri.preobrazhenski at gmail.com>
  Date:   2022-12-13 (Tue, 13 Dec 2022)

  Changed paths:
    M llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst
    M llvm/docs/AMDGPU/gfx8_hwreg.rst
    M llvm/docs/AMDGPU/gfx8_imask.rst
    A llvm/docs/AMDGPU/gfx8_imm16_0533c2.rst
    A llvm/docs/AMDGPU/gfx8_imm16_169952.rst
    R llvm/docs/AMDGPU/gfx8_imm16_73139a.rst
    R llvm/docs/AMDGPU/gfx8_imm16_a04fb3.rst
    M llvm/docs/AMDGPU/gfx8_label.rst
    R llvm/docs/AMDGPU/gfx8_m_254bcb.rst
    A llvm/docs/AMDGPU/gfx8_m_28b494.rst
    A llvm/docs/AMDGPU/gfx8_m_c141fc.rst
    R llvm/docs/AMDGPU/gfx8_m_f5d306.rst
    M llvm/docs/AMDGPU/gfx8_msg.rst
    R llvm/docs/AMDGPU/gfx8_sbase_010ce0.rst
    A llvm/docs/AMDGPU/gfx8_sbase_b0aa25.rst
    A llvm/docs/AMDGPU/gfx8_soffset_32c2a9.rst
    R llvm/docs/AMDGPU/gfx8_soffset_499d5b.rst
    R llvm/docs/AMDGPU/gfx8_soffset_ac5750.rst
    A llvm/docs/AMDGPU/gfx8_soffset_b5af46.rst
    A llvm/docs/AMDGPU/gfx8_srsrc_80eef6.rst
    R llvm/docs/AMDGPU/gfx8_srsrc_e73d16.rst
    M llvm/docs/AMDGPU/gfx8_tgt.rst
    M llvm/docs/AMDGPU/gfx8_type_deviation.rst
    A llvm/docs/AMDGPU/gfx8_vaddr_887f26.rst
    R llvm/docs/AMDGPU/gfx8_vaddr_e9b690.rst
    A llvm/docs/AMDGPU/gfx8_vdata_2d6239.rst
    R llvm/docs/AMDGPU/gfx8_vdata_325b78.rst
    A llvm/docs/AMDGPU/gfx8_vdata_4b260e.rst
    R llvm/docs/AMDGPU/gfx8_vdata_4d8ecf.rst
    A llvm/docs/AMDGPU/gfx8_vdata_629a92.rst
    A llvm/docs/AMDGPU/gfx8_vdata_84fab6.rst
    R llvm/docs/AMDGPU/gfx8_vdata_87fb90.rst
    R llvm/docs/AMDGPU/gfx8_vdata_a9eee3.rst
    A llvm/docs/AMDGPU/gfx8_vdata_aa5a53.rst
    A llvm/docs/AMDGPU/gfx8_vdata_ad559c.rst
    R llvm/docs/AMDGPU/gfx8_vdata_b2a787.rst
    R llvm/docs/AMDGPU/gfx8_vdata_c61803.rst
    A llvm/docs/AMDGPU/gfx8_vdst_0ae2f9.rst
    R llvm/docs/AMDGPU/gfx8_vdst_0b9599.rst
    A llvm/docs/AMDGPU/gfx8_vdst_2d89ba.rst
    R llvm/docs/AMDGPU/gfx8_vdst_3c54c3.rst
    R llvm/docs/AMDGPU/gfx8_vdst_3c6fb6.rst
    R llvm/docs/AMDGPU/gfx8_vdst_3d7dcf.rst
    A llvm/docs/AMDGPU/gfx8_vdst_4730df.rst
    R llvm/docs/AMDGPU/gfx8_vdst_5d50a1.rst
    A llvm/docs/AMDGPU/gfx8_vdst_6f591e.rst
    A llvm/docs/AMDGPU/gfx8_vdst_709347.rst
    R llvm/docs/AMDGPU/gfx8_vdst_7eb33e.rst
    A llvm/docs/AMDGPU/gfx8_vdst_81a6ed.rst
    A llvm/docs/AMDGPU/gfx8_vdst_829fc5.rst
    A llvm/docs/AMDGPU/gfx8_vdst_9c54fe.rst
    A llvm/docs/AMDGPU/gfx8_vdst_b61114.rst
    A llvm/docs/AMDGPU/gfx8_vdst_c360a5.rst
    A llvm/docs/AMDGPU/gfx8_vdst_d71f1c.rst
    A llvm/docs/AMDGPU/gfx8_vdst_d809e2.rst
    R llvm/docs/AMDGPU/gfx8_vdst_d85497.rst
    A llvm/docs/AMDGPU/gfx8_vdst_dd8a32.rst
    A llvm/docs/AMDGPU/gfx8_vdst_de9309.rst
    A llvm/docs/AMDGPU/gfx8_vdst_dfa6da.rst
    R llvm/docs/AMDGPU/gfx8_vdst_e0515f.rst
    R llvm/docs/AMDGPU/gfx8_vsrc_533a4e.rst
    A llvm/docs/AMDGPU/gfx8_vsrc_ba3116.rst
    M llvm/docs/AMDGPU/gfx8_waitcnt.rst

  Log Message:
  -----------
  [AMDGPU][GFX8][DOC][NFC] Update assembler syntax description

Summary of changes:
- Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205).
- Enable abs and neg modifiers for v_cndmask_b32 (https://reviews.llvm.org/D135900).
- Correct v_mov_b32_sdwa (it does not support abs and neg input modifiers yet).
- Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783).
- Minor corrections and improvements.