[all-commits] [llvm/llvm-project] a538d1: [TableGen][CodeEmitterGen] Allow local names for s...

[James Y Knight via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a538d1f13a1375c212c7018e36deab2cd896bf6e
      https://github.com/llvm/llvm-project/commit/a538d1f13a1375c212c7018e36deab2cd896bf6e
  Author: James Y Knight <jyknight at google.com>
  Date:   2022-09-24 (Sat, 24 Sep 2022)

  Changed paths:
    M llvm/lib/TableGen/Record.cpp
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/ARM/ARMInstrThumb2.td
    M llvm/utils/TableGen/CodeEmitterGen.cpp
    M llvm/utils/TableGen/CodeGenInstruction.cpp
    M llvm/utils/TableGen/CodeGenInstruction.h
    M llvm/utils/TableGen/DecoderEmitter.cpp

  Log Message:
  -----------
  [TableGen][CodeEmitterGen] Allow local names for sub-operands in a operand list.

These names can then be matched by name against 'bits' fields in a
record, to populate an instruction's encoding.

This does _not_ yet change DecoderEmitter to allow by-name matching of
sub-operands. Unlike the encoder, the decoder already defaulted to not
supporting positional matching, and backends had workarounds in place
for the missing decoding support.

Additionally, use this new capability to allow the ARM and AArch64
backends not to require any positional operand matching.

Differential Revision: https://reviews.llvm.org/D131003


  Commit: 5351878ba1963a84600df3a9e907b458b0529851
      https://github.com/llvm/llvm-project/commit/5351878ba1963a84600df3a9e907b458b0529851
  Author: James Y Knight <jyknight at google.com>
  Date:   2022-09-24 (Sat, 24 Sep 2022)

  Changed paths:
    M llvm/include/llvm/Target/Target.td
    M llvm/lib/Target/AMDGPU/AMDGPU.td
    M llvm/lib/Target/AMDGPU/R600.td
    M llvm/lib/Target/AVR/AVR.td
    M llvm/lib/Target/Lanai/Lanai.td
    M llvm/lib/Target/Mips/Mips.td
    M llvm/lib/Target/PowerPC/PPC.td
    M llvm/lib/Target/Sparc/Sparc.td
    M llvm/lib/Target/VE/VE.td
    M llvm/test/TableGen/InsufficientPositionalOperands.td
    A llvm/test/TableGen/MissingOperandField.td
    M llvm/utils/TableGen/CodeEmitterGen.cpp
    M llvm/utils/TableGen/DecoderEmitter.cpp

  Log Message:
  -----------
  [TableGen] Add useDeprecatedPositionallyEncodedOperands option.

Summary:
The existing undefined-bitfield-to-operand matching behavior is very
hard to understand, due to the combination of positional and named
matching. This can make it difficult to track down a bug in a target's
instruction definitions.

Over the last decade, folks have tried to work-around this in various
ways, but it's time to finally ditch the positional matching. With
https://reviews.llvm.org/D131003, there are no longer cases that
_require_ positional matching, and it's time to start removing usage
and support for it.

Therefore: add a (default-false) option, and set it to true only in
those targets that require positional matching today. Subsequent
changes will start cleaning up additional in-tree targets.

NOTE TO OUT OF TREE TARGET MAINTAINERS:

If this change breaks your build, you may restore the previous
behavior simply by adding:
  let useDeprecatedPositionallyEncodedOperands = 1;
to your target's InstrInfo tablegen definition. However, this is
temporary -- the option will be removed in the future.

If your target does not set 'decodePositionallyEncodedOperands', you
may thus start migrating to named operands. However, if you _do_
currently set that option, I recommend waiting until a subsequent
change lands, which adds decoder support for named sub-operands.

Differential Revision: https://reviews.llvm.org/D134073


Compare: https://github.com/llvm/llvm-project/compare/e657acd449a8...5351878ba196