[all-commits] [llvm/llvm-project] 3c70c8: [AggressiveInstCombine] Combine consecutive loads ...

[bipmis via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3c70c8c1df66500f67f77596b1e76cf0a8447ee5
      https://github.com/llvm/llvm-project/commit/3c70c8c1df66500f67f77596b1e76cf0a8447ee5
  Author: bipmis <biplob.mishra at arm.com>
  Date:   2022-09-23 (Fri, 23 Sep 2022)

  Changed paths:
    M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
    M llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll
    M llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll

  Log Message:
  -----------
  [AggressiveInstCombine] Combine consecutive loads which are being merged to form a wider load.

The patch simplifies some of the patterns as below

1. (ZExt(L1) << shift1) | (ZExt(L2) << shift2) -> ZExt(L3) << shift1
2. (ZExt(L1) << shift1) | ZExt(L2) -> ZExt(L3)

The pattern is indicative of the fact that the loads are being merged to a wider load and the only use of this pattern is with a wider load. In this case for a non-atomic/non-volatile loads reduce the pattern to a combined load which would improve the cost of inlining, unrolling, vectorization etc.

Differential Revision: https://reviews.llvm.org/D127392