[all-commits] [llvm/llvm-project] 32dc11: [VPlan] Only generate single instr for unpredicate...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 32dc1151e20dd20b89f8d6ab118c5c56df2e8dd9
      https://github.com/llvm/llvm-project/commit/32dc1151e20dd20b89f8d6ab118c5c56df2e8dd9
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-09-22 (Thu, 22 Sep 2022)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-illegal-type.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/illegal-type.ll
    M llvm/test/Transforms/LoopVectorize/X86/cost-model-assert.ll
    M llvm/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll
    M llvm/test/Transforms/LoopVectorize/X86/pr36524.ll
    M llvm/test/Transforms/LoopVectorize/X86/uniform_mem_op.ll
    M llvm/test/Transforms/LoopVectorize/pr44488-predication.ll
    M llvm/test/Transforms/LoopVectorize/pr47343-expander-lcssa-after-cfg-update.ll

  Log Message:
  -----------
  [VPlan] Only generate single instr for unpredicated stores of varying value to invariant address

This extends the previously added uniform store case to handle stores of loop varying values to a loop invariant address. Note that the placement of this code only allows unpredicated stores; this is important for correctness. (That is "IsPredicated" is always false at this point in the function.)

This patch does not include scalable types. The diff felt "large enough" as it were; I'll handle that in a separate patch. (It requires some changes to cost modeling.)

Differential Revision: https://reviews.llvm.org/D133580