[all-commits] [llvm/llvm-project] bf7c76: [RISCV] Improve support for vector fp_to_sint_sat/...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bf7c7696fe8fcef468d921d3174eccc186a3cd04
      https://github.com/llvm/llvm-project/commit/bf7c7696fe8fcef468d921d3174eccc186a3cd04
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-09-22 (Thu, 22 Sep 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
    M llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll
    M llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll

  Log Message:
  -----------
  [RISCV] Improve support for vector fp_to_sint_sat/uint_sat.

The default fixed vector legalization is to unroll. The default
scalable vector legalization is to clamp in the FP domain. The
RVV vfcvt instructions have saturating behavior so we can use them
directly. The only difference is that RVV instruction turn nan into
the max value, but the _SAT intrinsics want 0.

I'm only supporting 1 step of narrowing for now. I think we can
support more steps by using VNCLIP to saturate and narrower.

The only case that needs 2 steps of widening is f16->i64 which we can
do as f16->f32->i64.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D134400