[all-commits] [llvm/llvm-project] 94ebd7: MachineVerifier: Verify REG_SEQUENCE

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 94ebd7d9ff1776bbc94ca6ac82a783fa9d4eaa72
      https://github.com/llvm/llvm-project/commit/94ebd7d9ff1776bbc94ca6ac82a783fa9d4eaa72
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-09-22 (Thu, 22 Sep 2022)

  Changed paths:
    M llvm/lib/CodeGen/MachineOperand.cpp
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
    M llvm/test/CodeGen/AMDGPU/load-store-opt-dlc.mir
    M llvm/test/CodeGen/AMDGPU/load-store-opt-scc.mir
    M llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir
    A llvm/test/MachineVerifier/verify-reg-sequence.mir

  Log Message:
  -----------
  MachineVerifier: Verify REG_SEQUENCE

Somehow there was no verification of this, other than an ad-hoc
assertion in TwoAddressInstructions.