[all-commits] [llvm/llvm-project] 4f78e0: [AArch64] Lower scalar sqxtn intrinsics to use fp ...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4f78e022ee3d437f8aefc4d7adb8abe7bb33b9ac
      https://github.com/llvm/llvm-project/commit/4f78e022ee3d437f8aefc4d7adb8abe7bb33b9ac
  Author: David Green <david.green at arm.com>
  Date:   2022-09-21 (Wed, 21 Sep 2022)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsAArch64.td
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/test/CodeGen/AArch64/arm64-arith-saturating.ll

  Log Message:
  -----------
  [AArch64] Lower scalar sqxtn intrinsics to use fp registers

The llvm.aarch64.neon.scalar.sqxtn.i32.i64 intrinsics take and return
integer types, but operate on fp registers. This can create some
inefficiencies in their lowering, where the registers are converted to
fp a little too late. This patch adds lowering for the intrinsics,
creating bitcasts to/from fp types to allow nicer folding later when the
instructions are selected, especially around insert/extracts.

Differential Revision: https://reviews.llvm.org/D134024