[all-commits] [llvm/llvm-project] b982ba: [AMDGPU][GFX11] Use VGPR_32_Lo128 for VOP1, 2, C

[Joe Nash via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b982ba2a6e0f11340b4e75d1d4eba9ff62a81df7
      https://github.com/llvm/llvm-project/commit/b982ba2a6e0f11340b4e75d1d4eba9ff62a81df7
  Author: Joe Nash <Joseph.Nash at amd.com>
  Date:   2022-09-20 (Tue, 20 Sep 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
    M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
    M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
    M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SIModeRegister.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
    M llvm/lib/Target/AMDGPU/VOP1Instructions.td
    M llvm/lib/Target/AMDGPU/VOP2Instructions.td
    M llvm/lib/Target/AMDGPU/VOP3Instructions.td
    M llvm/lib/Target/AMDGPU/VOPCInstructions.td
    M llvm/lib/Target/AMDGPU/VOPInstructions.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
    M llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
    M llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
    R llvm/test/CodeGen/AMDGPU/gfx10-shrink-mad-fma.mir
    A llvm/test/CodeGen/AMDGPU/gfx10-twoaddr-fma.mir
    A llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir
    M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
    A llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.mir
    M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/preserve-hi16.ll
    A llvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir
    M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
    A llvm/test/CodeGen/AMDGPU/true16-ra-f128-fail.mir
    A llvm/test/CodeGen/AMDGPU/true16-ra-pre-gfx11-regression-test.mir
    M llvm/test/CodeGen/AMDGPU/twoaddr-fma.mir
    M llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
    A llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
    A llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
    A llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
    A llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
    A llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s
    A llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s
    A llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s
    A llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s

  Log Message:
  -----------
  [AMDGPU][GFX11] Use VGPR_32_Lo128 for VOP1,2,C

    Due to the encoding changes in GFX11, we had a hack in place that
    disables the use of VGPRs above 128. This patch removes the need for
    that hack.

    We introduce a new register class VGPR_32_Lo128 which is used for 16-bit
    operands of VOP1, VOP2, and VOPC instructions. This register class only has the
    low 128 VGPRs, but is otherwise identical to VGPR_32. Therefore, 16-bit VOP1,
    VOP2, and VOPC instructions are correctly limited to use the first 128
    VGPRs, while the other instructions can freely use all 256.

    We introduce new pseduo-instructions used on GFX11 which have the suffix
    t16 (True 16) to use the VGPR_32_Lo128 register class.

Reviewed By: foad, rampitec, #amdgpu

Differential Revision: https://reviews.llvm.org/D133723