[all-commits] [llvm/llvm-project] 820604: [DAG] SimplifyDemandedVectorElts - add MULHS/MULHU...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8206044183ed0cd134ac40f9c7f31ad68efd567e
      https://github.com/llvm/llvm-project/commit/8206044183ed0cd134ac40f9c7f31ad68efd567e
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-09-19 (Mon, 19 Sep 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
    M llvm/test/CodeGen/X86/combine-sdiv.ll
    M llvm/test/CodeGen/X86/combine-udiv.ll
    M llvm/test/CodeGen/X86/pmulh.ll
    M llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
    M llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll

  Log Message:
  -----------
  [DAG] SimplifyDemandedVectorElts - add MULHS/MULHU handling to existing MUL/AND handling

Allows to determine known zero elements, which particularly helps simplification of DIV/REM by constant patterns