[all-commits] [llvm/llvm-project] 2e8863: [AMDGPU] Don't shrink VOP3 instructions pre-RA on ...

[Jay Foad via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2e8863b6a11f12d31490bc054da4d47c6adc8143
      https://github.com/llvm/llvm-project/commit/2e8863b6a11f12d31490bc054da4d47c6adc8143
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2022-09-13 (Tue, 13 Sep 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
    M llvm/test/CodeGen/AMDGPU/gfx10-shrink-mad-fma.mir
    M llvm/test/CodeGen/AMDGPU/shrink-instructions-implicit-vcclo.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll

  Log Message:
  -----------
  [AMDGPU] Don't shrink VOP3 instructions pre-RA on GFX10+

In GFX10, there is no advantage to shrinking these instructions pre-RA,
so this just saves a bit of work.

In GFX11 there is an advantage to *not* shrinking them pre-RA, because
the register classes for 16-bit operands are less restrictive in the
VOP3 form than in the shrunk form. This patch is a prerequisite for
actually setting up those register classes correctly for 16-bit vs
non-16-bit operands.

Differential Revision: https://reviews.llvm.org/D133769