[all-commits] [llvm/llvm-project] 8e132c: [LegalizeTypes][ARM][X86] Change ExpandIntRes_ABS ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8e132c5c1d4cfb6c48b91370666cffcc2af77b61
      https://github.com/llvm/llvm-project/commit/8e132c5c1d4cfb6c48b91370666cffcc2af77b61
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-03-07 (Mon, 07 Mar 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/test/CodeGen/ARM/iabs.ll
    M llvm/test/CodeGen/Thumb2/mve-abs.ll
    M llvm/test/CodeGen/Thumb2/mve-vabdus.ll
    M llvm/test/CodeGen/X86/abs.ll
    M llvm/test/CodeGen/X86/iabs.ll
    M llvm/test/CodeGen/X86/neg-abs.ll
    M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected

  Log Message:
  -----------
  [LegalizeTypes][ARM][X86] Change ExpandIntRes_ABS to use sra+xor+sub.

Previously we used sra+add+xor if ADDCARRY is supported. This changes
to sra+xor+sub is SUBCARRY is available.

This is consistent with the recent change to the default expansion
in LegalizeDAG.

Differential Revision: https://reviews.llvm.org/D121039


  Commit: 845bfcede1e90e678719a7c57a6e43c069682c2c
      https://github.com/llvm/llvm-project/commit/845bfcede1e90e678719a7c57a6e43c069682c2c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-03-07 (Mon, 07 Mar 2022)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

  Log Message:
  -----------
  [RISCV] Rename 'SplatOperand' to 'ScalarOperand'. NFC

vslide1up/down have this flag set, but the value isn't a splat.
Rename for clarity.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D121037


Compare: https://github.com/llvm/llvm-project/compare/a0b4aaffac9d...845bfcede1e9