[all-commits] [llvm/llvm-project] 3d4e83: [RISCV] With Zbb, fold (sext_inreg (abs X)) -> (ma...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3d4e83f17dbefb991fc6896005b5e4aa6d412985
      https://github.com/llvm/llvm-project/commit/3d4e83f17dbefb991fc6896005b5e4aa6d412985
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rv64zbb.ll

  Log Message:
  -----------
  [RISCV] With Zbb, fold (sext_inreg (abs X)) -> (max X, (negw X))

With Zbb, abs is expanded to (max X, neg) by default. If X has 33 or
more sign bits, we can expand it a little early using negw instead of
neg to save a sext_inreg. If X started as a 32 bit value, type
legalization would have inserted a sext before the abs so X having
33 sign bits should always be true.

Note: I've used ISD::FREEZE here since we increase the number of uses.
Our default expansion for ABS doesn't do that, but I think that's a bug.

We can't do this with custom type legalization because ISD::FREEZE
doesn't propagate sign bits so later DAG combine won't expand be
able to see optmize it.

Alives2 https://alive2.llvm.org/ce/z/Gx3RNe

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D120597