[all-commits] [llvm/llvm-project] 88bc29: [RISCV] Introduce a RISCV CondCode enum instead of...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 88bc29f5f2c08301d43b9fc33d8098faff161fd1
      https://github.com/llvm/llvm-project/commit/88bc29f5f2c08301d43b9fc33d8098faff161fd1
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-08-08 (Sun, 08 Aug 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.h
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/select-optimize-multiple.mir

  Log Message:
  -----------
  [RISCV] Introduce a RISCV CondCode enum instead of using ISD:SET* in MIR. NFC

Previously we converted ISD condition codes to integers and stored
them directly in our MIR instructions. The ISD enum kind of belongs
to SelectionDAG so that seems like incorrect layering.

This patch instead uses a CondCode node on RISCV::SELECT_CC until
isel and then converts it from ISD encoding to a RISCV specific value.
This value can be converted to/from the RISCV branch opcodes in the
RISCV namespace.

My larger motivation is to possibly support a microarchitectural
feature of some CPUs where a short forward branch over a single
instruction can be predicated internally. This will require a new
pseudo instruction for select that needs to carry a branch condition
and live probably until RISCVExpandPseudos. At that point it can be
expanded to control flow without other instructions ending up in the
predicated basic block. Using an ISD encoding in RISCVExpandPseudos
doesn't seem like correct layering.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D107400