[all-commits] [llvm/llvm-project] 660693: [RISCV] Remove -target-abi from half-bitmanip-dagc...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6606936322c4dcbead997a3fda13507e758afb8d
      https://github.com/llvm/llvm-project/commit/6606936322c4dcbead997a3fda13507e758afb8d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-08-08 (Sun, 08 Aug 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll

  Log Message:
  -----------
  [RISCV] Remove -target-abi from half-bitmanip-dagcombines.ll.

This should be testing the custom ISD nodes we use for passing
half values in GPRs.

We should optimize these to integer operations, but we currently
don't.


  Commit: 2f3b738960e919d0138c8c4e9813a9155c193398
      https://github.com/llvm/llvm-project/commit/2f3b738960e919d0138c8c4e9813a9155c193398
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-08-08 (Sun, 08 Aug 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll

  Log Message:
  -----------
  [RISCV] Add optimizations for FMV_X_ANYEXTH similar to FMV_X_ANYEXTW_RV64.

This enables the fneg and fabs combines we have for FMV_X_ANYEXTW_RV64.


Compare: https://github.com/llvm/llvm-project/compare/88bc29f5f2c0...2f3b738960e9