[all-commits] [llvm/llvm-project] cfbb92: [SDAG] Fix pow2 assumption when splitting vectors

[Carl Ritson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cfbb92441f17d1f5a9d9c3e195646df4117cb0ca
      https://github.com/llvm/llvm-project/commit/cfbb92441f17d1f5a9d9c3e195646df4117cb0ca
  Author: Carl Ritson <carl.ritson at amd.com>
  Date:   2021-06-11 (Fri, 11 Jun 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

  Log Message:
  -----------
  [SDAG] Fix pow2 assumption when splitting vectors

When reducing vector builds to shuffles it possible that
the DAG combiner may try to extract invalid subvectors.

This happens as the existing code assumes vectors will be power
of 2 sizes, which is already untrue, but becomes more noticable
with v6 and v7 types.
Specifically the existing code assumes that half PowerOf2Ceil of
a given vector index will fit twice into a given vector.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D103880


  Commit: 2c2d2922a24b7fa8a92f38d9043ab476d330210d
      https://github.com/llvm/llvm-project/commit/2c2d2922a24b7fa8a92f38d9043ab476d330210d
  Author: Carl Ritson <carl.ritson at amd.com>
  Date:   2021-06-11 (Fri, 11 Jun 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/ValueTypes.td
    M llvm/include/llvm/Support/MachineValueType.h
    M llvm/lib/CodeGen/ValueTypes.cpp
    M llvm/utils/TableGen/CodeGenTarget.cpp

  Log Message:
  -----------
  [ValueTypes] Define MVTs for v6i32, v6f32, v7i32, v7f32

For use in AMDGPU selection DAG.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D103881


Compare: https://github.com/llvm/llvm-project/compare/b35a842581f0...2c2d2922a24b