[all-commits] [llvm/llvm-project] b35a84: [RISCV] Add test cases that show failure to use so...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b35a842581f089daa57dd7e6b78ccb08d92709b2
      https://github.com/llvm/llvm-project/commit/b35a842581f089daa57dd7e6b78ccb08d92709b2
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-06-10 (Thu, 10 Jun 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll

  Log Message:
  -----------
  [RISCV] Add test cases that show failure to use some W instructions if they are proceeded by a load. NFC

The loads end up becoming sextload/zextload which prevent our
isel patterns from finding the sign_extend_inreg or AND instruction
we need.

The easiest way to fix this is to use computeKnownBits or
ComputeNumSignBits in our isel matching to catch this.