[all-commits] [llvm/llvm-project] 670edf: [AArch64][GlobalISel] Fix incorrectly generating u...

[Amara Emerson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 670edf3ee0045ce007f2f6aec94a2c3344c5682e
      https://github.com/llvm/llvm-project/commit/670edf3ee0045ce007f2f6aec94a2c3344c5682e
  Author: Amara Emerson <amara at apple.com>
  Date:   2021-06-10 (Thu, 10 Jun 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir

  Log Message:
  -----------
  [AArch64][GlobalISel] Fix incorrectly generating uxtw/sxtw for addressing modes.

When the extend is from 8 or 16 bits, the addressing modes don't support those
extensions, but we weren't checking that and therefore always generated the 32->64b
extension mode. Fun.

Differential Revision: https://reviews.llvm.org/D104070