[all-commits] [llvm/llvm-project] 14bd44: [AArch64][SVEIntrinsicOpts] Factor out redundant S...

[Joe Ellis via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 14bd44edc6afbb2bf7c823750b3d0f4e15fb02c8
      https://github.com/llvm/llvm-project/commit/14bd44edc6afbb2bf7c823750b3d0f4e15fb02c8
  Author: Joe Ellis <joe.ellis at arm.com>
  Date:   2021-03-16 (Tue, 16 Mar 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/SVEIntrinsicOpts.cpp
    A llvm/test/CodeGen/AArch64/sve-fmul-idempotency.ll
    A llvm/test/CodeGen/AArch64/sve-mul-idempotency.ll

  Log Message:
  -----------
  [AArch64][SVEIntrinsicOpts] Factor out redundant SVE mul/fmul intrinsics

This commit implements an IR-level optimization to eliminate idempotent
SVE mul/fmul intrinsic calls. Currently, the following patterns are
captured:

    fmul  pg  (dup_x  1.0)  V  =>  V
    mul   pg  (dup_x  1)    V  =>  V

    fmul  pg  V  (dup_x  1.0)  =>  V
    mul   pg  V  (dup_x  1)    =>  V

    fmul  pg  V  (dup  v  pg  1.0)  =>  V
    mul   pg  V  (dup  v  pg  1)    =>  V

The result of this commit is that code such as:

    1  #include <arm_sve.h>
    2
    3  svfloat64_t foo(svfloat64_t a) {
    4    svbool_t t = svptrue_b64();
    5    svfloat64_t b = svdup_f64(1.0);
    6    return svmul_m(t, a, b);
    7  }

will lower to a nop.

This commit does not capture all possibilities; only the simple cases
described above. There is still room for further optimisation.

Differential Revision: https://reviews.llvm.org/D98033