[all-commits] [llvm/llvm-project] a33ce0: [RISCV] Improve i32 UADDSAT/USUBSAT on RV64.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a33ce06cf59a31c96a484a11b526392d9f8c9548
      https://github.com/llvm/llvm-project/commit/a33ce06cf59a31c96a484a11b526392d9f8c9548
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-03-16 (Tue, 16 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/uadd_sat.ll
    M llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
    M llvm/test/CodeGen/RISCV/usub_sat.ll
    M llvm/test/CodeGen/RISCV/usub_sat_plus.ll

  Log Message:
  -----------
  [RISCV] Improve i32 UADDSAT/USUBSAT on RV64.

The default promotion uses zero extends that become shifts. We
cam use sign extend instead which is better for RISCV.

I've used two different implementations based on whether we
have minu/maxu instructions.

Differential Revision: https://reviews.llvm.org/D98683