[all-commits] [llvm/llvm-project] 09966a: [RISCV] Add an additional remw test to rv64m-exhau...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 09966a66ffd08a04306c754ce20420d05109771a
      https://github.com/llvm/llvm-project/commit/09966a66ffd08a04306c754ce20420d05109771a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-20 (Sat, 20 Feb 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll

  Log Message:
  -----------
  [RISCV] Add an additional remw test to rv64m-exhaustive-w-insts.ll. NFC

This adds the IR for this C code

int32_t foo(uint16_t x, int16_t y) {
  x %= y;
  return x;
}

Note the dividend is unsigned and the divisor is signed. C type
promotion rules will extend them and use a 32-bit srem and the
function returns a 32-bit result.

We fail to use remw for this case. The zero extended input has
enough sign bits, but we won't consider (i64 AssertZext X, i16) in
the sexti32 isel pattern.

We also end up with a extra shifts to zero upper bits on the result.
computeKnownBits knew the result was positive before type legalization
and allowed the SIGN_EXTEND to become ZERO_EXTEND. But after promoting
to i64 we no longer know that bit 31 (and all bits above it) should
be 0.