[all-commits] [llvm/llvm-project] cf3455: [RISCV] Enable PrimaryKeyEarlyOut on RISCVVPseudos...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cf34559104d3531e98e16ea242b777f18d5f95cf
      https://github.com/llvm/llvm-project/commit/cf34559104d3531e98e16ea242b777f18d5f95cf
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-18 (Thu, 18 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

  Log Message:
  -----------
  [RISCV] Enable PrimaryKeyEarlyOut on RISCVVPseudosTable.

This table is queried in RISCVMCInstLower without knowing
whether the instruction is a vector pseudo. Due to the way the
binary search works, we have to do log2(tablesize) checks just
to determine a non-vector instruction isn't in the table.

Conveniently, all the vector pseudos are pretty tightly
packed within the internal instruction enum. By enabling the
PrimaryKeyEarlyOut, tablegen will emit a check against the
beginning and end of the table before doing the binary search.
This gives a quick early out on the search for the majority
of non-vector instructions.

Differential Revision: https://reviews.llvm.org/D97016


  Commit: 8ed3bbbcc35233dce19f77208c2f3d21c3f68902
      https://github.com/llvm/llvm-project/commit/8ed3bbbcc35233dce19f77208c2f3d21c3f68902
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-18 (Thu, 18 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

  Log Message:
  -----------
  [RISCV] Split zvlsseg searchable table into 4 separate tables. Index by properties rather than intrinsic ID.

Intrinsic ID is a 32-bit value which made each row of the table 4
byte aligned. The remaining fields used 5 bytes. This meant 3 bytes
of padding per row.

This patch breaks the table into 4 separate tables and indexes them
by properties we know about the intrinsic. NF, masked,
strided, ordered, etc. The indexed load/store tables have no
padding in their rows now.

All together this reduces the size of llc binary by ~28K.

I'm considering adding similar tables for isel of non-segment
load/store as well to cut down the size of the isel table and
probably improve our isel performance. Those tables would need to
indexed from intrinsics, IR loads/stores, gathers/scatters, and
RISCVISD opcodes. So having a table that can be indexed without using
intrinsic ID is more flexible.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D96894


Compare: https://github.com/llvm/llvm-project/compare/c4ad878acb62...8ed3bbbcc352