[all-commits] [llvm/llvm-project] 8bad8a: [AArch64][SVE] Add patterns to generate FMLA/FMLS/...

[Bradley Smith via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8bad8a43c339729bf722d519c3a25708a54bc205
      https://github.com/llvm/llvm-project/commit/8bad8a43c339729bf722d519c3a25708a54bc205
  Author: Bradley Smith <bradley.smith at arm.com>
  Date:   2021-02-18 (Thu, 18 Feb 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
    M llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll
    A llvm/test/CodeGen/AArch64/sve-fp-combine.ll
    M llvm/test/CodeGen/AArch64/sve-fp.ll

  Log Message:
  -----------
  [AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD

Adjust generateFMAsInMachineCombiner to return false if SVE is present
in order to combine fmul+fadd into fma. Also add new pseudo instructions
so as to select the most appropriate of FMLA/FMAD depending on register
allocation.

Depends on D96599

Differential Revision: https://reviews.llvm.org/D96424