[all-commits] [llvm/llvm-project] a8d9d5: [AMDGPU] gfx90a support

Stanislav Mekhanoshin via All-commits all-commits at lists.llvm.org
Wed Feb 17 16:02:33 PST 2021 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a8d9d50762c42d726274d3f1126ec97ff96e2a22
      https://github.com/llvm/llvm-project/commit/a8d9d50762c42d726274d3f1126ec97ff96e2a22
  Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
  Date:   2021-02-17 (Wed, 17 Feb 2021)

  Changed paths:
    M clang/docs/ClangCommandLineReference.rst
    M clang/include/clang/Basic/BuiltinsAMDGPU.def
    M clang/include/clang/Basic/Cuda.h
    M clang/include/clang/Driver/Options.td
    M clang/lib/Basic/Cuda.cpp
    M clang/lib/Basic/Targets/AMDGPU.cpp
    M clang/lib/Basic/Targets/NVPTX.cpp
    M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
    M clang/test/CodeGenOpenCL/amdgpu-features.cl
    M clang/test/CodeGenOpenCL/builtins-amdgcn-mfma.cl
    M clang/test/Driver/amdgpu-features.c
    M clang/test/Driver/amdgpu-macros.cl
    M clang/test/Driver/amdgpu-mcpu.cl
    M clang/test/Driver/cuda-bad-arch.cu
    M clang/test/Driver/hip-toolchain-features.hip
    M clang/test/Misc/target-invalid-cpu-note.c
    A clang/test/SemaOpenCL/builtins-amdgcn-error-gfx90a-param.cl
    M llvm/docs/AMDGPUUsage.rst
    M llvm/include/llvm/BinaryFormat/ELF.h
    M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
    M llvm/include/llvm/Support/AMDHSAKernelDescriptor.h
    M llvm/include/llvm/Support/TargetParser.h
    M llvm/lib/Object/ELFObjectFile.cpp
    M llvm/lib/ObjectYAML/ELFYAML.cpp
    M llvm/lib/Support/TargetParser.cpp
    M llvm/lib/Target/AMDGPU/AMDGPU.td
    M llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h
    M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
    M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
    M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
    M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
    M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    M llvm/lib/Target/AMDGPU/BUFInstructions.td
    M llvm/lib/Target/AMDGPU/DSInstructions.td
    M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
    M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
    M llvm/lib/Target/AMDGPU/FLATInstructions.td
    M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
    M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
    M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
    M llvm/lib/Target/AMDGPU/GCNProcessors.td
    M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
    M llvm/lib/Target/AMDGPU/GCNRegPressure.h
    M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
    M llvm/lib/Target/AMDGPU/GCNSubtarget.h
    M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
    M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
    M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
    M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
    M llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
    M llvm/lib/Target/AMDGPU/MIMGInstructions.td
    M llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp
    M llvm/lib/Target/AMDGPU/SIDefines.h
    M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
    M llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
    M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
    M llvm/lib/Target/AMDGPU/SIInstrFormats.td
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
    M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
    M llvm/lib/Target/AMDGPU/SIProgramInfo.h
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/lib/Target/AMDGPU/SISchedule.td
    M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
    M llvm/lib/Target/AMDGPU/VOP1Instructions.td
    M llvm/lib/Target/AMDGPU/VOP2Instructions.td
    M llvm/lib/Target/AMDGPU/VOP3Instructions.td
    M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
    M llvm/lib/Target/AMDGPU/VOPInstructions.td
    M llvm/test/Analysis/CostModel/AMDGPU/fadd.ll
    M llvm/test/Analysis/CostModel/AMDGPU/fma.ll
    M llvm/test/Analysis/CostModel/AMDGPU/fmul.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.s96.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.s96.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.fadd-with-ret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.fadd.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
    M llvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir
    A llvm/test/CodeGen/AMDGPU/acc-ldst.ll
    M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
    A llvm/test/CodeGen/AMDGPU/adjust-writemask-vectorized.ll
    A llvm/test/CodeGen/AMDGPU/agpr-csr.ll
    M llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
    M llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
    M llvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir
    M llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir
    M llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
    M llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
    M llvm/test/CodeGen/AMDGPU/bundle-latency.mir
    A llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
    M llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
    M llvm/test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir
    M llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
    A llvm/test/CodeGen/AMDGPU/coalesce-vgpr-alignment.ll
    M llvm/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
    M llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir
    M llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
    A llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
    M llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
    M llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
    M llvm/test/CodeGen/AMDGPU/dead-lane.mir
    M llvm/test/CodeGen/AMDGPU/dead_copy.mir
    M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
    A llvm/test/CodeGen/AMDGPU/dpp64_combine.ll
    A llvm/test/CodeGen/AMDGPU/dpp64_combine.mir
    M llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
    M llvm/test/CodeGen/AMDGPU/endpgm-dce.mir
    M llvm/test/CodeGen/AMDGPU/expand-si-indirect.mir
    M llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
    M llvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir
    M llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
    M llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir
    M llvm/test/CodeGen/AMDGPU/fma.f64.ll
    M llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir
    M llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
    M llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
    M llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
    M llvm/test/CodeGen/AMDGPU/fold-multiple.mir
    M llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
    A llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
    A llvm/test/CodeGen/AMDGPU/gfx90a-enc.ll
    M llvm/test/CodeGen/AMDGPU/global-atomics-fp.ll
    M llvm/test/CodeGen/AMDGPU/hard-clauses.mir
    M llvm/test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir
    M llvm/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir
    M llvm/test/CodeGen/AMDGPU/hazard-in-bundle.mir
    M llvm/test/CodeGen/AMDGPU/hazard-inlineasm.mir
    M llvm/test/CodeGen/AMDGPU/hazard-pass-ordering.mir
    M llvm/test/CodeGen/AMDGPU/hazard-recognizer-meta-insts.mir
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
    M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
    M llvm/test/CodeGen/AMDGPU/insert-skips-flat-vmem.mir
    M llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir
    M llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir
    M llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
    M llvm/test/CodeGen/AMDGPU/lds-branch-vmem-hazard.mir
    M llvm/test/CodeGen/AMDGPU/limit-coalesce.mir
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.fadd.gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.fadd.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.gfx90a.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.i8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
    A llvm/test/CodeGen/AMDGPU/llvm.pow-gfx9.ll
    M llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
    A llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir
    M llvm/test/CodeGen/AMDGPU/mai-hazards.mir
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-addrspace.mir
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir
    M llvm/test/CodeGen/AMDGPU/memory_clause.mir
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    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx10.mir
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    M llvm/test/CodeGen/AMDGPU/regbank-reassign.mir
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    M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
    A llvm/test/CodeGen/AMDGPU/reserved-reg-in-clause.mir
    A llvm/test/CodeGen/AMDGPU/reserved-vgpr-tuples.mir
    M llvm/test/CodeGen/AMDGPU/s_code_end.ll
    M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
    M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
    M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
    M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
    M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-gfx9.mir
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    M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
    M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
    M llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
    M llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
    M llvm/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir
    M llvm/test/CodeGen/AMDGPU/subvector-test.mir
    M llvm/test/CodeGen/AMDGPU/syncscopes.ll
    A llvm/test/CodeGen/AMDGPU/tgsplit.ll
    M llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
    A llvm/test/CodeGen/AMDGPU/twoaddr-fma-f64.mir
    M llvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir
    A llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir
    M llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
    M llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vmem-vcc-hazard.mir
    A llvm/test/CodeGen/AMDGPU/waitcnt-agpr.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-loop-irreducible.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-loop-single-basic-block.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-meta-instructions.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-overflow.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-preexisting.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-vmem-waw.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt.mir
    M llvm/test/CodeGen/AMDGPU/wqm.mir
    M llvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll
    M llvm/test/CodeGen/MIR/AMDGPU/load-store-opt-dlc.mir
    A llvm/test/CodeGen/MIR/AMDGPU/load-store-opt-scc.mir
    M llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
    M llvm/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
    M llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir
    M llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
    M llvm/test/MC/AMDGPU/atomic-fadd-insts.s
    A llvm/test/MC/AMDGPU/dpp64.s
    A llvm/test/MC/AMDGPU/gfx90a_asm_features.s
    A llvm/test/MC/AMDGPU/gfx90a_err.s
    A llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
    M llvm/test/MC/AMDGPU/hsa-diag-v3.s
    A llvm/test/MC/AMDGPU/hsa-gfx90a-v3.s
    A llvm/test/MC/AMDGPU/mai-gfx90a.s
    A llvm/test/MC/AMDGPU/mimg-gfx90a.s
    A llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s
    M llvm/test/MC/AMDGPU/vop_dpp.s
    A llvm/test/MC/Disassembler/AMDGPU/dpp64.txt
    A llvm/test/MC/Disassembler/AMDGPU/gfx90a_dasm_features.txt
    A llvm/test/MC/Disassembler/AMDGPU/gfx90a_ldst_acc.txt
    A llvm/test/MC/Disassembler/AMDGPU/mai-gfx90a.txt
    A llvm/test/MC/Disassembler/AMDGPU/mimg_gfx90a.txt
    M llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
    A llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f32.ll
    M llvm/test/tools/llvm-readobj/ELF/amdgpu-elf-headers.test
    M llvm/tools/llvm-readobj/ELFDumper.cpp

  Log Message:
  -----------
  [AMDGPU] gfx90a support

Differential Revision: https://reviews.llvm.org/D96906

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