[all-commits] [llvm/llvm-project] 7ba2e1: [RISCV] Add support for fixed vector floating poin...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7ba2e1c6011eeb1b91ce3f5d8fa7187b7518e77a
      https://github.com/llvm/llvm-project/commit/7ba2e1c6011eeb1b91ce3f5d8fa7187b7518e77a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-15 (Mon, 15 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll

  Log Message:
  -----------
  [RISCV] Add support for fixed vector floating point setcc.

This is annoying because the condition code legalization belongs
to LegalizeDAG, but our custom handler runs in Legalize vector ops
which occurs earlier.

This adds some of the mask binary operations so that we can combine
multiple compares that we need for expansion.

I've also fixed up RISCVISelDAGToDAG.cpp to handle copies of masks.

This patch contains a subset of the integer setcc patch as well.
That patch is dependent on the integer binary ops patch. I'll rebase
based on what order the patches go in.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D96567