[llvm-dev] union of register classes

[Matt Arsenault via llvm-dev]

> On Jun 27, 2019, at 08:54, David Callahan via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> 
>                def PSrc : registerclass<”ns”, [Type1, Type2], 8, (add P0…., S0…)>

I think this should be specified as (add PSrc, Src), rather than adding the same register elements to each

>                def Pop : RegisterOperand<Prc> { }
>                def FOO : OperandWithDefaults<Type1, (ops P0)>
> 
II don’t think tablegen is smart enough to infer the type here. I think this should work if you explicitly list (ops (Type1 P0)), but I also haven’t seen OperandWithDefaults used with something that isn’t an immediate.

-Matt
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