[llvm-dev] union of register classes

David Callahan via llvm-dev llvm-dev at lists.llvm.org
Thu Jun 27 05:54:12 PDT 2019

Suppose I have a target system with two different register classes which hold different values,  let us refer to them as Prc and Src, and individual elements P0,P1,… and S0,S1… respectively

Now I have an instruction which has a field that takes either a Prc or an Src.

If I create a third register class which combines all of the individual registers and has both types, then I get an error such as

error: Value #0 of OperandWithDefaultOps  ‘’FOO” doesn't have a concrete type!

Where effectively I had

               def Prc : registerclass<’”ns”, [Type1], 8 (add P0, … )>

               def Src : registerclass<’”ns”, [Type2], 8 (add S0, … )>

               def PSrc : registerclass<”ns”, [Type1, Type2], 8, (add P0…., S0…)>

               def Pop : RegisterOperand<Prc> { }

               def FOO : OperandWithDefaults<Type1, (ops P0)>

What guidance or examples are there for approaching this kind of problem?



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