[llvm-dev] How to use tablegen to describe branches where the status register is implicitly set?
Matthias Braun via llvm-dev
llvm-dev at lists.llvm.org
Mon Jan 29 17:23:14 PST 2018
You could try instruction bundles (though bundling before RA is very uncommon and I'm at least aware of some cases where the regallocator cannot handle when the last instruction (bundle) of a function produces a new value because it tries to place a spill behind the definition.
Or you model it with a pseudo that expands into a sub with 0 / br (like cmp/branch on other targets) and try to eliminate the sub via late peepholes where possible.
> On Jan 29, 2018, at 12:48 PM, Ahmed Samara via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> I'm working on writing a backend for a processor that only has one Branch instruction, a BRnzp, where it branches on a status register (NZP: Negative, Zero, Positive) based on what the result of the last arithmetic operation was. It's implicitly set, nowhere in userspace.
> Basically, it follows the format of:
> ADD ....
> BR 010 ... (Branches if the result of the ADD was zero).
> Unconditional branches are given as a 111 argument.
> How can I use tablegen to describe this in a way that the scheduler also understands that it's 'attached' to the last instruction?
> Ahmed Samara
> M.S. Computer Engineering
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
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