[llvm-dev] How to use tablegen to describe branches where the status register is implicitly set?
Krzysztof Parzyszek via llvm-dev
llvm-dev at lists.llvm.org
Tue Jan 30 06:38:36 PST 2018
You can add the status register as an implicit use to all such branches,
and as an implicit def to all instructions that modify it.
Check "Defs" and "Uses" in the definition of "Instruction" in
On 1/29/2018 2:48 PM, Ahmed Samara via llvm-dev wrote:
> I'm working on writing a backend for a processor that only has one
> Branch instruction, a BRnzp, where it branches on a status register
> (NZP: Negative, Zero, Positive) based on what the result of the last
> arithmetic operation was. It's implicitly set, nowhere in userspace.
> Basically, it follows the format of:
> ADD ....
> BR 010 ... (Branches if the result of the ADD was zero).
> Unconditional branches are given as a 111 argument.
> How can I use tablegen to describe this in a way that the scheduler also
> understands that it's 'attached' to the last instruction?
> Ahmed Samara
> M.S. Computer Engineering
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
More information about the llvm-dev