[llvm-dev] How to use tablegen to describe branches where the status register is implicitly set?
Ahmed Samara via llvm-dev
llvm-dev at lists.llvm.org
Mon Jan 29 12:48:55 PST 2018
I'm working on writing a backend for a processor that only has one Branch
instruction, a BRnzp, where it branches on a status register (NZP:
Negative, Zero, Positive) based on what the result of the last arithmetic
operation was. It's implicitly set, nowhere in userspace.
Basically, it follows the format of:
BR 010 ... (Branches if the result of the ADD was zero).
Unconditional branches are given as a 111 argument.
How can I use tablegen to describe this in a way that the scheduler also
understands that it's 'attached' to the last instruction?
M.S. Computer Engineering
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