[llvm-dev] Meaning of loads/stores marked both atomic and volatile
Paweł Batko via llvm-dev
llvm-dev at lists.llvm.org
Mon Nov 20 07:25:09 PST 2017
I read about volatile and atomic modifiers in the docs, and I feel
they make sense to me individually.
However, I noticed that store and load instructions can be
marked as both volatile and atomic.
What's the use case for using both volatile and atomic on an
instruction? Isn't it the case that atomic implies volatile? I guess
it isn't, but I don't understand why.
I'm guessing that while both volatile and atomic restrict reorderings,
volatile prevents any kind of load or store elimination optimizations
but atomic doesn't have such guarantee.
E.g. I suspect that an atomic load, which can be implemented as a pair
of a plain load and a fence instruction, can be optimized away to only
a fence instruction. If it was both volatile and atomic, then such
optimization would've been illegal.
In other words, probably very imprecisely, volatile tells the compiler
what it cannot do while atomic tells the cpu what it should do to
guarantee certain memory model (and it'd also imply extra constraints
on what a compiler can do).
My other guess is that it's only to order 'atomic' instruction with
'volatile' instruction, thus the former becomes 'atomic volatile'.
I'd appreciate links to any resources on the topic.
More information about the llvm-dev