[llvm-dev] Meaning of loads/stores marked both atomic and volatile
Tim Northover via llvm-dev
llvm-dev at lists.llvm.org
Mon Nov 20 07:41:20 PST 2017
On 20 November 2017 at 15:25, Paweł Batko via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> What's the use case for using both volatile and atomic on an
> instruction? Isn't it the case that atomic implies volatile?
You pretty much got the semantics right straight after this. The
compiler isn't allowed to add, remove or reorder volatile accesses but
it is for some atomics if no other thread could prove it had.
There are only a couple of valid uses for volatile these days (since
everyone realised that using it for inter-thread synchronization was a
bad idea); the main one is talking to memory-mapped hardware in an OS
kernel or something. I could see someone using an atomic volatile
there for something like talking to a DMA engine: write your buffer
with normal instructions, then do a store-volatile-release to tell the
DMA to start copying. I've not checked if that actually works for any
architectures I know about though.
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