[llvm-dev] Expanding SDNodes
Krzysztof Parzyszek via llvm-dev
llvm-dev at lists.llvm.org
Mon Nov 20 04:42:35 PST 2017
On 11/20/2017 5:31 AM, Liad Mordekoviz via llvm-dev wrote:
>> Combining: t6: i32 = zero_extend t3
>> Creating constant: t10: i32 = Constant<65535>
>> Creating new node: t11: i32 = and t2, Constant:i32<65535>
>> ... into: t11: i32 = and t2, Constant:i32<65535>
> I was wondering if there is a way to expand the t6 node to “zext t3” so
> it won’t combine?
> (Maybe defining some pattern on my backend’s tablegen or something like
The DAG combiner will expand zero-extends into ands, and in your
selection patterns you can simply match a corresponding and with the
bitmask instead of a zext. You can even write a PatFrag to serve as a
macro for that.
Another option is that you can lower zero-extend to a custom operation
for your target. DAG combiner won't do anything with it, and then you
can match it directly in the patterns.
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