[llvm-dev] HW loads wider than int

Davis, Alan via llvm-dev llvm-dev at lists.llvm.org
Wed Jan 11 12:04:33 PST 2017

> So you want to make int 64 bit? Or you want int to stay 32 bit, long to be 64 bit but sign extend int 32 bit to 64?

Int is 32, long is 64. Assuming 'int *p' the same HW load instruction covers int = *p and long = *p.

I can have separate names for the 32-bit subregisters, but then I think I would need two forms of the load, one to target each. I was hoping the selector would be smart enough to user wider instruction forms for narrower types when the upper bits are unneeded. 

> ARM64 is like this. I suggest having a look at that backend (lib/Target/AArch64) and how it deals with implicit zeroing of the upper bits of the X registers.

I did look a bit at AArch64. The difference is that AArch64 explicitly has 32-bit (W) and 64-bit (X) forms of ldr, and the .td appropriately models them as 2 instructions: ldrw and ldrx. In our case there is one ldw instruction, that loads 32 bits and sign/zero extends it. It would be used for either a 32-bit load, with the upper bits remaining unused, or a 32-to-64 sextload. If possible I'd like to model that with one instruction in the .td.

I will spend more time looking at AArch64 though, as I don't yet fully understand all the subtleties of extending, promoting, and so on.


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