[llvm-dev] HW loads wider than int
Tim Northover via llvm-dev
llvm-dev at lists.llvm.org
Wed Jan 11 12:16:12 PST 2017
On 11 January 2017 at 12:04, Davis, Alan via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> I did look a bit at AArch64. The difference is that AArch64 explicitly has 32-bit (W) and 64-bit (X) forms of ldr, and the .td appropriately models them as 2 instructions: ldrw and ldrx. In our case there is one ldw instruction, that loads 32 bits and sign/zero extends it. It would be used for either a 32-bit load, with the upper bits remaining unused, or a 32-to-64 sextload. If possible I'd like to model that with one instruction in the .td.
I think the AArch64 situation is actually a lot closer than you think.
There are 3 relevant variants:
* load 32-bits, zero extend into 64-bit register (AArch64 calls this
a plain LDRW since it's indistinguishable in effect from that).
* load 32-bits, sign extend to 64 (LDRSW on AArch64).
* load 64-bits (LDRX on AArch64).
The first one is what gets used for an i32 load, though if you wanted
to be perverse you could probably use any of them since the difference
is unobservable on 32-bits.
I assume you've got similar, which would just make it a matter of
naming the instructions. If you've actually combined LDRW and LDRSW
into a single instruction then presumably there's some second operand
that specifies whether to sign/zero extend, and you can set that
correctly when writing patterns.
The separate registers are definitely a bigger problem though. Mips
might actually be a better model there, since from my very hazy memory
it spells the 32 & 64-bit versions the same too. It also seems to have
separate 64-bit LLVM registers (e.g. V0 and V0_64).
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