[llvm-dev] HW loads wider than int

Tim Northover via llvm-dev llvm-dev at lists.llvm.org
Wed Jan 11 10:50:33 PST 2017

On 11 January 2017 at 10:24, Jim Grosbach via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> ARM64 is like this. I suggest having a look at that backend (lib/Target/AArch64) and how it deals with implicit zeroing of the upper bits of the X registers.

ARM64 has a separate name for the registers as 32-bit values though
(W0-W30 rather than X0-X30). I could easily see DAG ISel throwing a
fit without that.

First thing I'd try would be adding the 64-bit registers as a valid
class for i32 ("addRegisterClass(MVT::i32, GPR64)"). If that works,
you're good to go; if not, it should be possible add fake 32-bit
registers and just print them the same as the 64-bit ones at the end.
The nastiest hackery would be in the AsmParser, which may or may not
be important.



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