[llvm-dev] Specify special cases of delay slots in the back end
Hal Finkel via llvm-dev
llvm-dev at lists.llvm.org
Fri Feb 3 12:25:30 PST 2017
You can program a post-RA scheduler which will return NoopHazard in the
appropriate circumstances. You can look at the PowerPC target (e.g.
lib/Target/PowerPC/PPCHazardRecognizers.cpp) as an example.
On 02/02/2017 05:03 PM, Alex Susu via llvm-dev wrote:
> I see there is little information on specifying instructions with
> delay slots.
> So could you please tell me how can I insert NOPs (BEFORE or after
> an instruction) or how to make an aware instruction scheduler in order
> to avoid miscalculations due to the delay slot effect?
> More exactly, I have the following constraints on my (SIMD)
> - certain stores or loads, must be executed 1 cycle after the
> instruction generating their input operands ends. For example, if I have:
> R1 = R2 + R3
> LS[R10] = R1 // this will not produce the correct result
> because it does not see the updated value of R1 from the previous
> To make this code execute correctly we need to insert a NOP:
> R1 = R2 + R3
> NOP // or other instruction to fill the delay slot
> LS[R10] = R1
> - a compare instruction requires to add a NOP after it, before
> the predicated block (something like a conditional JMP instruction)
> Thank you,
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory
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