[llvm-dev] Specify special cases of delay slots in the back end

[Alex Susu via llvm-dev]

   Hello.
     I see there is little information on specifying instructions with delay slots.
     So could you please tell me how can I insert NOPs (BEFORE or after an instruction) or 
how to make an aware instruction scheduler in order to avoid miscalculations due to the 
delay slot effect?

     More exactly, I have the following constraints on my (SIMD) processor:
       - certain stores or loads, must be executed 1 cycle after the instruction 
generating their input operands ends. For example, if I have:
          R1 = R2 + R3
          LS[R10] = R1 // this will not produce the correct result because it does not see 
the updated value of R1 from the previous instruction
        To make this code execute correctly we need to insert a NOP:
          R1 = R2 + R3
          NOP // or other instruction to fill the delay slot
          LS[R10] = R1

       - a compare instruction requires to add a NOP after it, before the predicated block 
(something like a conditional JMP instruction) starts.


   Thank you,
     Alex