[llvm-dev] how to allocate consecutive register?
Bruce Hoult via llvm-dev
llvm-dev at lists.llvm.org
Fri Sep 9 13:23:53 PDT 2016
There are other CPUs with similar restrictions. You could look at how they
handle it. An example which springs to mind is ARM A32 LDRD and STRD
(load/store two consecutive registers). I think some other architectures do
the same for operations which return two results, such as div/mod or
On Fri, Sep 9, 2016 at 3:56 PM, Ruiling Song via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> The gpu target I am working on requires the 'value' and 'address'
> operands of memory store instruction in consecutive register. Anybody has
> - Ruiling
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
-------------- next part --------------
An HTML attachment was scrubbed...
More information about the llvm-dev