[llvm-dev] TableGen register class

Xiangyang Guo via llvm-dev llvm-dev at lists.llvm.org
Tue Feb 2 20:17:19 PST 2016


Assume I define registers R0...R15 and two register classes RegA and RegB.
RegA contains R0 to R7 while RegB contains R0 to R15.

Then I check the machine instruction, it seems that in some cases, the
%vreg0 belongs to RegB; in other cases %vreg1 belongs to RegA_RegB. Can you
tell me how TableGen decides which is which? At first, I guess &verg0 will
be assigned by R8 to R15 only so that %vreg0 belongs to RegB. But it seems
my guess is wrong because %verg0 can also be assigned by R0.

Any input is appreciable.


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