[llvm-dev] TableGen register class

Matt Arsenault via llvm-dev llvm-dev at lists.llvm.org
Tue Feb 2 20:36:47 PST 2016

> On Feb 2, 2016, at 20:17, Xiangyang Guo via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> Hi,
> Assume I define registers R0...R15 and two register classes RegA and RegB. RegA contains R0 to R7 while RegB contains R0 to R15.
> Then I check the machine instruction, it seems that in some cases, the %vreg0 belongs to RegB; in other cases %vreg1 belongs to RegA_RegB. Can you tell me how TableGen decides which is which? At first, I guess &verg0 will be assigned by R8 to R15 only so that %vreg0 belongs to RegB. But it seems my guess is wrong because %verg0 can also be assigned by R0.
> Any input is appreciable.
> Regards,
> Xiangyang
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TableGen does not directly make the decision on what class to use for virtual registers, only the constraints on the operand. InstrEmitter ultimately makes this decision, using a combination of factors including the register class you specified for a specific type, whether the class is allocatable, and satisfying the operand register classes defined as a property of the instruction. The register classes defined for the instruction's operands in TableGen influences the selected class. See InstrEmitter::CreateVirtualRegisters and other related functions.


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